The present invention relates to electronic testing and more particularly, to a testing configuration and an interface assembly for use with a logic analyzer.
Printed circuit boards (PCBs) and the electronic components on the PCBs are tested to detect faults and to ensure proper operation of the PCBs. Greater demands for speed and bandwidth in the computer and telecommunications industries have resulted in PCBs with higher densities of electronic components and signals. A motherboard used in a router or switch, for example, includes a large number of application specific integrated circuit (ASIC) devices. As a result of the smaller size and increased number of components on a single PCB, proper testing of the PCB and the electronic components has become more critical and more difficult.
One way of testing PCBs with electronic components is using a logic analyzer system. The logic analyzer system connects to signal points on the PCB and monitors the signals executed by the electronic components on the PCB. Engineers and technicians can use the logic analyzer system to analyze the signal patterns and detect faults in the electronic components. Testing using a logic analyzer is preferably conducted at or near the operating speed of the PCB to approach an xe2x80x9cat speedxe2x80x9d observation opportunity for the signals. To approach an xe2x80x9cat speedxe2x80x9d observation, testing is typically conducted under operating conditions with the PCB located in an assembled system (e.g., in a chassis).
The previous approach to conducting this type of xe2x80x9cat speedxe2x80x9d test using a logic analyzer system was to solder individual wires to the PCB signal points and transfer those wires to the analyzer connectors. One of the drawbacks of this approach is having to connect the individual wires to a large number of test points that are difficult to access on a dense PCB. When testing multiple PCBs, the changeover between PCBs is time consuming and tedious.
One technique for testing a PCB with a large number of test points uses a test fixture including an array of probes, often referred to as a xe2x80x9cbed of nails.xe2x80x9d In the conventional xe2x80x9cbed of nailsxe2x80x9d test fixture, the probes, at one end, contact test points on the PCB. At the opposite end, the probes are connected to the test equipment using single point wiring. Thus, the conventional xe2x80x9cbed of nailsxe2x80x9d test fixture still requires a significant amount of wiring when used to test PCBs with a large number of test points. Traditional xe2x80x9cbed of nailsxe2x80x9d test fixtures are associated with, and targeted towards, industry standard platforms for Manufacturing Defect Analyzer (MDA) and In-Circuit testers. These testers and fixtures generally are not suited for xe2x80x9cat speedxe2x80x9d implementations, for example, because of problems with signal integrity, and would not be compatible through form and fit to a custom chassis interface.
Accordingly, there is a need for a testing configuration and a logic analyzer interface assembly that speeds the test process and aids in approaching xe2x80x9cat speedxe2x80x9d testing of a PCB and that allows a quick changeover between multiple PCBs having a large number of test points.
In accordance with one aspect of the present invention, a logic analyzer interface assembly is used with a unit under test (UUT,) having a plurality of UUT contact points in a predefined pattern. The interface assembly comprises an interface board having a plurality of interface contact points on a primary side arranged to match the predefined pattern of the UUT contact points. A plurality of analyzer connectors on a secondary side of the interface board are electrically connected to the contact points. The assembly also comprises a transfer interface including at least one probe plate and a plurality of probes extending through and floating freely in the probe plate. Each of the probes includes a barrel and a single spring loaded plunger extending from the barrel. The plunger of each of the probes contacts the UUT contact points and the barrel of each of the probes contacts the interface contact points on the interface board. At least one probe retention plate is positioned over at least one side of the probe plate for retaining the probes in the probe plate.
In accordance with another aspect of the present invention, a logic analyzer testing configuration comprises a sandwiched testing assembly and a chassis for receiving the testing assembly. The sandwiched testing assembly is dimensioned to fit into a rack in the chassis and the UUT is allowed to mate with back panel connections of the chassis as in a normal operating configuration such that testing of the UUT is conducted within the chassis. The sandwiched testing assembly comprises the unit under test (UUT), the interface board, and the transfer interface sandwiched between the UUT and the interface board. The transfer interface includes at least one probe plate and a plurality of probes extending through the probe plate. Each of the probes contacts one of the UUT contact points on the UUT and one of the interface contact points on the interface board. Analyzer cables are connected to the analyzer connectors on the interface board, and media cables are connected to the UUT.
According to a further aspect of the present invention, a method of interfacing a unit under test (UUT) to a logic analyzer comprises providing a unit under test (UUT) having a plurality of electronic components and a plurality of UUT contact points in a predefined pattern and providing a logic analyzer interface assembly. The UUT is mounted to the logic analyzer interface assembly to form a sandwiched testing assembly such that each of the probes contacts one of the UUT contact points on the UUT corresponding to the interface contact points on the interface board. The sandwiched testing assembly is inserted into a rack in a chassis, UUT cables are connected to the UUT, and logic analyzer cables are connected to the logic analyzer interface assembly.